A master-slave relationship refers to a communication protocol where one device, the master, has unidirectional control over another device, the slave. Upon establishment of such a relationship, the direction of control is typically from the master device to the slave device. A common example of such a relationship is a slave device, such as a memory device, coupled to a master central processing unit (CPU) via a parallel bus, wherein the slave device is generally under full control of the master CPU. To avoid adverse affects, such as “hanging” the bus as a result of an interrupted bus transaction, error recovery activities of the slave device are generally controlled to varying degrees by the master CPU.
Traditionally, the slave device detects and reports errors to the master CPU. Depending on the system, the master CPU may then initiate an error recovery by the slave device, instruct the slave device as to a specific type of error recovery operation to perform, or carry out the recovery operation itself. However, as slave devices continue to become more complex and more intelligent, error recovery becomes more complex as well, with each device having specific error recovery requirements. Consequently, error recovery operations of slave devices may potentially become too complex for the master CPU to intervene and, at the very least, consume increased amounts of master CPU processing time that could be spent performing other tasks.